1. Technical Field
Generally, the disclosed embodiments relate to integrated circuits, and, more particularly, to power management of multiple compute units sharing memory, such as cache memory.
2. Description of the Related Art
A computer system comprising two or more compute units (e.g., cores of a central processing unit (CPU)) can place those compute units into a lower power state when they are not needed to perform user- or system-requested operations. Placing unneeded compute units into a lower power state may reduce power consumption and heat generation by the computer system, thereby reducing operating expenses of the computer system and extending the service life of the computer system or components thereof. It is common for a computer system to contain a central power management unit (PMU) to orchestrate the low power transitions for each of the compute units within the system. Typically, the PMU can make requests directly to each compute unit to independently power down and power up.
At times, the compute units may share a common memory, such as a cache memory. When a compute unit is directed to power down, one issue to be addressed is the problem of shutting down any associated cache memory that may be shared with another compute unit. Commonly, when a compute unit is directed to power down, the compute unit will save off its architectural state to some memory retention area, flush its caches of all modified data (i.e., complete any writing of modified data from dirty cache locations to main memory and evict the modified data from the cache), and then signal its low power readiness to the PMU. At this point, the PMU will turn off power to that compute unit. When the PMU requires the compute unit to power up (e.g., exit a lower power state or enter a normal power state) to service a process, the PMU will turn on power to the compute unit, and the compute unit will restore its architectural state from the memory retention area and start servicing the process.
A shared cache unit (SCU) is sometimes used within e.g. a CPU system so that all the included compute units can share cache resources. If an existing CPU system design were to add a SCU to its architecture, it can be beneficial for the PMU to directly interact with the SCU via one interface and for that SCU to interact with all the CPU cores directly. However, with such a topology, a legacy PMU might not “understand” the extra level of hierarchy containing the SCU, thereby possibly leading to incomplete or ineffectual power management. Reengineering a PMU/SCU/multiple cores system to understand a hierarchy containing a SCU would be a relatively complicated task which the person of ordinary skill in the art would wish to avoid. Further, engineering other elements of the computer system to aid the PMU in power management of an SCU/multiple cores system runs the risk of requiring a large number of interactions of possibly long latency, which could undesirably slow down power management transitions.